Conventionally, Japanese Patent Application Publication No. H11-266017 (which corresponds to U.S. Pat. No. 6,573,534) discloses a power MOSFET as a silicon carbide semiconductor device operated in an accumulation mode. In this power MOSFET, an N− conductive type layer is disposed on a surface of a N− conductive type base region and disposed under a gate oxide film made of SiO2 so that the N− conductive type layer connects between a N+ conductive type source region and a N+ conductive type epitaxial layer (i.e., a N+ conductive type epi-layer).
The silicon carbide semiconductor device having the above construction becomes an off-state when the N− conductive type layer becomes a depletion layer before a voltage is applied to the gate electrode. When the voltage is applied to the gate electrode, a channel region is formed at an interface between the N− conductive type layer and the gate insulation film. The channel region extends from the N+ conductive type source region 4a, 4b to two directions of the N− conductive type drift regions. Thus, the device switches from the off-state to an on-state so that the device flows current therethrough.
Thus, the above power MOSFET is operated in an accumulation mode so that the channel is induced without reversing the conductive type of the channel formation layer. Thus, the above MOSFET is capable of enlarging channel mobility so that an on-state resistance is reduced, compared with a MOSFET operated in a reverse mode for reversing the conductive type.
In the above power MOSFET having the above construction, the gate insulation film is made of an oxide film (i.e., SiO2). However, an interface state is formed between the gate insulation film and the N− conductive type layer for forming the channel in a case where the gate insulation film is composed of the oxide film. Further, the interface state is formed near a conduction band of energy space, in which an electron current flows. Therefore, the charged interface state affects current flow so that the channel mobility is reduced. Further, the on-state resistance of the power MOSFET is increased. Thus, it is confirmed that this problem is occurred.
Further, in general, an eight-degree offset substrate is used in a process for manufacturing a silicon carbide semiconductor substrate. A film is epitaxially grown on the eight-degree offset substrate by a step growth method.
However, the eight-degree offset surface of the SiC substrate is not a stable surface. Therefore, a defect caused by polishing is easily generated when a wafer is processed. Thus, it is difficult to form homogeneous surface state in a wafer surface. Therefore, for example, a device fault is occurred at a portion of a substrate having bad surface state such as a defect caused by polishing in a MOS transistor. The MOS transistor includes a source region, a drain region, a gate oxide film, and a gate electrode formed on a surface portion of the substrate. In detail, when the defect caused by polishing is disposed on the surface of the substrate, current leakage is easily occurred at the gate oxide film.
Further, when a device is formed in the SiC substrate after epitaxial growth, for example, a crystal defect due to the defect caused by polishing on the surface of the substrate may generate in the epitaxial layer of the device (i.e., diode), so that current leakage (i.e., a PN junction leakage) is easily occurred. The device has the epitaxial layer on the substrate, in which a P conductive type region is formed, and has an anode electrode and a cathode electrode.